This invention relates to semiconductor integrated circuit random access memories (RAM), and more particularly the invention relates to improved control of spare column lines in such memories.
The semiconductor memory is organized in a matrix defined by word lines and bit lines organized in rows and columns. A cell in the memory array is addressed by a Y or column select address and an X or row select address.
Often a column line in a memory can be defective. Heretofore, spare column lines have been provided for replacing defective column select lines so that the memory device does not have to be scrapped. Usually each spare column line is dedicated to one sub-array and is not useable throughout the memory. For example, in a memory with 256 column lines, eight spare column lines might be provided with each spare column line dedicated for use in a sub-array of only 32 column lines.
In synchronous graphics dynamic random access memories (SGRAM), column select addresses include information in addition to the line address, and special logic in predecoders is required to re-format and identify the address. Heretofore, column spare decoders have included the logic necessary to decode the Y addresses. Further, some prior art spare column line decoders consume power even when a spare has not been selected.